Implementation of NoC on FPGA with Area and Power Optimization

On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working wa...

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Bibliographic Details
Main Authors:	Momil Ijaz, Huma Urooj, Muhammad Sethi
Format:	Article
Language:	English
Published:	European Alliance for Innovation (EAI) 2019-03-01
Series:	EAI Endorsed Transactions on Context-aware Systems and Applications
Subjects:	Network on chip node switching packet crossbar
Online Access:	https://eudl.eu/pdf/10.4108/eai.23-5-2019.158953

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spelling	doaj-bf41b69bec5041e69bb9ba264b71cfdb2020-11-24T22:06:25ZengEuropean Alliance for Innovation (EAI)EAI Endorsed Transactions on Context-aware Systems and Applications2409-00262019-03-0161610.4108/eai.23-5-2019.158953Implementation of NoC on FPGA with Area and Power OptimizationMomil Ijaz0Huma Urooj1Muhammad Sethi2Department of Computer Systems Engineering, University of Engineering and Technology, Peshawar, PakistanDepartment of Computer Systems Engineering, University of Engineering and Technology, Peshawar, PakistanDepartment of Computer Systems Engineering, University of Engineering and Technology, Peshawar, PakistanOn-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.https://eudl.eu/pdf/10.4108/eai.23-5-2019.158953Network on chipnodeswitchingpacketcrossbar
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Momil Ijaz Huma Urooj Muhammad Sethi
spellingShingle	Momil Ijaz Huma Urooj Muhammad Sethi Implementation of NoC on FPGA with Area and Power Optimization EAI Endorsed Transactions on Context-aware Systems and Applications Network on chip node switching packet crossbar
author_facet	Momil Ijaz Huma Urooj Muhammad Sethi
author_sort	Momil Ijaz
title	Implementation of NoC on FPGA with Area and Power Optimization
title_short	Implementation of NoC on FPGA with Area and Power Optimization
title_full	Implementation of NoC on FPGA with Area and Power Optimization
title_fullStr	Implementation of NoC on FPGA with Area and Power Optimization
title_full_unstemmed	Implementation of NoC on FPGA with Area and Power Optimization
title_sort	implementation of noc on fpga with area and power optimization
publisher	European Alliance for Innovation (EAI)
series	EAI Endorsed Transactions on Context-aware Systems and Applications
issn	2409-0026
publishDate	2019-03-01
description	On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.
topic	Network on chip node switching packet crossbar
url	https://eudl.eu/pdf/10.4108/eai.23-5-2019.158953
work_keys_str_mv	AT momilijaz implementationofnoconfpgawithareaandpoweroptimization AT humaurooj implementationofnoconfpgawithareaandpoweroptimization AT muhammadsethi implementationofnoconfpgawithareaandpoweroptimization
_version_	1725823927073112064

Implementation of NoC on FPGA with Area and Power Optimization

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