A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders
During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2019-04-01
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| Series: | Information |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2078-2489/10/4/151 |