A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders
During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC...
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doaj-c1ff41fa1b6546c293efc736c82114c72020-11-25T00:55:41ZengMDPI AGInformation2078-24892019-04-0110415110.3390/info10040151info10040151A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional EncodersGabriele Meoni0Gianluca Giuffrida1Luca Fanucci2Department of Information Engineering, University of Pisa, Via Girolamo Caruso, 16, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, Via Girolamo Caruso, 16, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, Via Girolamo Caruso, 16, 56122 Pisa, ItalyDuring the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder.https://www.mdpi.com/2078-2489/10/4/151recursive systematic convolutional encoderparallelismFPGAhigh throughput |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Gabriele Meoni Gianluca Giuffrida Luca Fanucci |
spellingShingle |
Gabriele Meoni Gianluca Giuffrida Luca Fanucci A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders Information recursive systematic convolutional encoder parallelism FPGA high throughput |
author_facet |
Gabriele Meoni Gianluca Giuffrida Luca Fanucci |
author_sort |
Gabriele Meoni |
title |
A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders |
title_short |
A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders |
title_full |
A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders |
title_fullStr |
A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders |
title_full_unstemmed |
A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders |
title_sort |
high throughput hardware architecture for parallel recursive systematic convolutional encoders |
publisher |
MDPI AG |
series |
Information |
issn |
2078-2489 |
publishDate |
2019-04-01 |
description |
During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder. |
topic |
recursive systematic convolutional encoder parallelism FPGA high throughput |
url |
https://www.mdpi.com/2078-2489/10/4/151 |
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