Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications. This article explores the connection between the physical structure of a device-level silicon controlled rectifier (SCR) and high-fai...

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Bibliographic Details
Main Authors: Yang Wang, Xiangliang Jin, Yan Peng, Jun Luo, Zeyu Zhong, Jun Yang
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
CMOS process
CMOS technology
electron devices
Online Access:https://ieeexplore.ieee.org/document/9279212/

Internet

https://ieeexplore.ieee.org/document/9279212/

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