Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

• Main Authors: Yang Wang, Xiangliang Jin, Yan Peng, Jun Luo, Zeyu Zhong, Jun Yang
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Access
• Subjects: CMOS process; CMOS technology; electron devices
• Online Access: https://ieeexplore.ieee.org/document/9279212/

As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications. This article explores the connection between the physical structure of a device-level silicon controlled rectifier (SCR) and high-failure ESD characteristics. The gate-controlled silicon controlled rectifier (GCSCR) based on the gate control effect is fabricated using the 0.18μm standard bipolar complementary-metal-oxide-semiconductor double-diffused-metal-oxide-semiconductor (BCD) process. The ESD characteristics of the device are analyzed by technology computer aided design (TCAD) simulation and equivalent circuits. The transmission line pulse (TLP) is used to test the performance of the device. The results show that when the gate length is 4μm, the failure current of the device is only 1.56A. When the gate length is 1μm, the trigger voltage and the holding voltage of the device are 24.4V and 21.1V respectively, and the failure current is 34.94A. According to the test results of the above devices, it can be concluded that the current release mode of GCSCR with different gate sizes significantly affects the ESD characteristics of the device.