Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Packet processing performance of Network Function Virtualization (NFV)-aware environment depends on the memory access performance of commercial-off-the-shelf (COTS) hardware systems. Table lookup is a typical example of packet processing, which has a significant dependence on memory access performan...

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Bibliographic Details
Main Authors: Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Communication systems
memory architecture
network function virtualization
performance analysis
queueing analysis
Online Access:https://ieeexplore.ieee.org/document/9039620/

Internet

https://ieeexplore.ieee.org/document/9039620/

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