Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM
Packet processing performance of Network Function Virtualization (NFV)-aware environment depends on the memory access performance of commercial-off-the-shelf (COTS) hardware systems. Table lookup is a typical example of packet processing, which has a significant dependence on memory access performan...
Main Authors: | , , , |
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Format: | Article |
Language: | English |
Published: |
IEEE
2020-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9039620/ |