Efficient Hardware Implementation of the LEDAcrypt Decoder

Efficient Hardware Implementation of the LEDAcrypt Decoder

This work describes an efficient implementation of the iterative decoder that is the main part of the decryption stage in the LEDAcrypt cryptosystem, recently proposed for post-quantum cryptography based on low-density parity-check (LDPC) codes. The implementation we present exploits the structure o...

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Bibliographic Details
Main Authors: Kristjane Koleci, Paolo Santini, Marco Baldi, Franco Chiaraluce, Maurizio Martina, Guido Masera
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Applied cryptography
post-quantum cryptography
hardware design
ASIC
FPGA
bit-flipping decoding
Online Access:https://ieeexplore.ieee.org/document/9417170/

Internet

https://ieeexplore.ieee.org/document/9417170/

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