FIR Filter Implementation for High-Performance Application in a High-End FPGA
In this paper a high-performance application which uses multiple 48k tap FIR filters is presented. Due to its size, complexity and restrictions such as real-time, small latency and large memory bandwidth, the filter was implemented in UltraScale+, a high-end FPGA from Xilinx. The system was verified...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Telecommunications Society, Academic Mind
2019-07-01
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| Series: | Telfor Journal |
| Subjects: | |
| Online Access: |
http://journal.telfor.rs/Published/Vol11No1/Vol11No1_A8.pdf
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