Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures
Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS proce...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Online Access: | https://ieeexplore.ieee.org/document/9072133/ |