Validation of a Real-time AVS Encoder on FPGA
A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize va...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IFSA Publishing, S.L.
2014-01-01
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| Series: | Sensors & Transducers |
| Subjects: | |
| Online Access: | http://www.sensorsportal.com/HTML/DIGEST/january_2014/Vol_163/P_1811.pdf |