Validation of a Real-time AVS Encoder on FPGA
A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize va...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IFSA Publishing, S.L.
2014-01-01
|
| Series: | Sensors & Transducers |
| Subjects: | |
| Online Access: | http://www.sensorsportal.com/HTML/DIGEST/january_2014/Vol_163/P_1811.pdf |
| id |
doaj-cd1007501ad64fb4a115683d7e3932ca |
|---|---|
| record_format |
Article |
| spelling |
doaj-cd1007501ad64fb4a115683d7e3932ca2020-11-24T20:53:41ZengIFSA Publishing, S.L.Sensors & Transducers2306-85151726-54792014-01-011631128134Validation of a Real-time AVS Encoder on FPGAQun Fang Yuan0Xin Liu1Yao Li Wang2Student Recruitment and Work Placement Office, Taiyuan University of Technology, Taiyuan, 030024, ChinaCollege of Information Engineering, Taiyuan University of Technology, Taiyuan, 030024, ChinaCollege of Information Engineering, Taiyuan University of Technology, Taiyuan, 030024, ChinaA whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize various encoding module and to ensure the efficient operation of the pipeline. Through the simulation of ISE software and the verification of Xilinx Vritex-4 pro platform, it can be seen that the highest working frequency can be up to 110 MHz, meeting the requirements of the whole I frame real- time encoding of AVS in CIF resolution. http://www.sensorsportal.com/HTML/DIGEST/january_2014/Vol_163/P_1811.pdfAVSEncoderFPGA. |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Qun Fang Yuan Xin Liu Yao Li Wang |
| spellingShingle |
Qun Fang Yuan Xin Liu Yao Li Wang Validation of a Real-time AVS Encoder on FPGA Sensors & Transducers AVS Encoder FPGA. |
| author_facet |
Qun Fang Yuan Xin Liu Yao Li Wang |
| author_sort |
Qun Fang Yuan |
| title |
Validation of a Real-time AVS Encoder on FPGA |
| title_short |
Validation of a Real-time AVS Encoder on FPGA |
| title_full |
Validation of a Real-time AVS Encoder on FPGA |
| title_fullStr |
Validation of a Real-time AVS Encoder on FPGA |
| title_full_unstemmed |
Validation of a Real-time AVS Encoder on FPGA |
| title_sort |
validation of a real-time avs encoder on fpga |
| publisher |
IFSA Publishing, S.L. |
| series |
Sensors & Transducers |
| issn |
2306-8515 1726-5479 |
| publishDate |
2014-01-01 |
| description |
A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize various encoding module and to ensure the efficient operation of the pipeline. Through the simulation of ISE software and the verification of Xilinx Vritex-4 pro platform, it can be seen that the highest working frequency can be up to 110 MHz, meeting the requirements of the whole I frame real- time encoding of AVS in CIF resolution.
|
| topic |
AVS Encoder FPGA. |
| url |
http://www.sensorsportal.com/HTML/DIGEST/january_2014/Vol_163/P_1811.pdf |
| work_keys_str_mv |
AT qunfangyuan validationofarealtimeavsencoderonfpga AT xinliu validationofarealtimeavsencoderonfpga AT yaoliwang validationofarealtimeavsencoderonfpga |
| _version_ |
1716796501243461632 |