COMPARISON OF INSTRUCTION SCHEDULING AND REGISTER ALLOCATION FOR MIPS AND HPL-PD ARCHITECTURE FOR EXPLOITATION OF INSTRUCTION LEVEL PARALLELISM

COMPARISON OF INSTRUCTION SCHEDULING AND REGISTER ALLOCATION FOR MIPS AND HPL-PD ARCHITECTURE FOR EXPLOITATION OF INSTRUCTION LEVEL PARALLELISM

The integrated approaches for instruction scheduling and register allocation have been promising area of research for code generation and compiler optimization. In this paper we have proposed an integrated algorithm for instruction scheduling and register allocation and implemented it for compiler...

Full description

Bibliographic Details
Main Author: Rajendra Kumar
Format: Article
Language:English
Published: Zibeline International 2018-01-01
Series:Engineering Heritage Journal
Subjects:
ILP
Instruction Scheduling
Register Allocation
Trimaran Simulator
Parallelilsm
Online Access:https://enggheritage.com/archives/2gwk2018/2gwk2018-04-08.pdf

Internet

https://enggheritage.com/archives/2gwk2018/2gwk2018-04-08.pdf

Similar Items