A Stepwise Rate-Compatible LDPC and Parity Management in NAND Flash Memory-Based Storage Devices

A Stepwise Rate-Compatible LDPC and Parity Management in NAND Flash Memory-Based Storage Devices

The storage capacity of the NAND flash memory has increased rapidly, and accordingly, the error rate for data writing and reading to the flash memory cell has also escalated. Error-correcting code (ECC) modules, such as low-density parity-check (LDPC), have been applied to flash controllers for erro...

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Bibliographic Details
Main Authors: Seung-Ho Lim, Jae-Bin Lee, Geon-Myeong Kim, Woo Hyun Ahn
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
NAND flash memory
flash storage
P/E cycle
RC LDPC
PCHK
parity
Online Access:https://ieeexplore.ieee.org/document/9186119/

Internet

https://ieeexplore.ieee.org/document/9186119/

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