A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm
The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs. We present the design of an efficient, pipelined floating-point datapath for calculating the logarithm function on reconfigurable devices. W...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/341510 |