High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination

In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed...

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Main Authors: Palash Sarker, Frank P. Kelly, Matthew Landi, Riley E. Vesto, Kyekyoon Kim
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Online Access:https://ieeexplore.ieee.org/document/9269357/
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spelling doaj-d4bf22d955d74de6a34cb1004c3c2e2e2021-03-29T18:52:50ZengIEEEIEEE Journal of the Electron Devices Society2168-67342021-01-019687810.1109/JEDS.2020.30399799269357High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge TerminationPalash Sarker0https://orcid.org/0000-0003-3376-2346Frank P. Kelly1https://orcid.org/0000-0001-7244-1583Matthew Landi2https://orcid.org/0000-0002-5803-7485Riley E. Vesto3https://orcid.org/0000-0001-8372-6146Kyekyoon Kim4https://orcid.org/0000-0002-1167-4882Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USAIn this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN <italic>p-i-n</italic> diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency &#x003E;98&#x0025; while maintaining a wide doping window of up to <inline-formula> <tex-math notation="LaTeX">$\sim \,\,5\times 10^{17}$ </tex-math></inline-formula>cm<sup>&#x2212;3</sup> at a minimum reverse blocking efficiency of &#x007E; 90&#x0025; extending well into high 10<sup>17</sup>cm<sup>&#x2212;3</sup> range (<inline-formula> <tex-math notation="LaTeX">$\sim \,\,8\times 10^{17}$ </tex-math></inline-formula>cm<sup>&#x2212;3</sup>). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.https://ieeexplore.ieee.org/document/9269357/Punchthrough (PT)reverse blocking efficiencysilicon nitride shadowed selective-area growth (SNS-SAG)space-modulated junction termination extension (SM-JTE)
collection DOAJ
language English
format Article
sources DOAJ
author Palash Sarker
Frank P. Kelly
Matthew Landi
Riley E. Vesto
Kyekyoon Kim
spellingShingle Palash Sarker
Frank P. Kelly
Matthew Landi
Riley E. Vesto
Kyekyoon Kim
High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination
IEEE Journal of the Electron Devices Society
Punchthrough (PT)
reverse blocking efficiency
silicon nitride shadowed selective-area growth (SNS-SAG)
space-modulated junction termination extension (SM-JTE)
author_facet Palash Sarker
Frank P. Kelly
Matthew Landi
Riley E. Vesto
Kyekyoon Kim
author_sort Palash Sarker
title High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination
title_short High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination
title_full High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination
title_fullStr High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination
title_full_unstemmed High-Performance GaN Vertical <italic>p-i-n</italic> Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination
title_sort high-performance gan vertical <italic>p-i-n</italic> diodes via silicon nitride shadowed selective-area growth and optimized fgr- and jte-based edge termination
publisher IEEE
series IEEE Journal of the Electron Devices Society
issn 2168-6734
publishDate 2021-01-01
description In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN <italic>p-i-n</italic> diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency &#x003E;98&#x0025; while maintaining a wide doping window of up to <inline-formula> <tex-math notation="LaTeX">$\sim \,\,5\times 10^{17}$ </tex-math></inline-formula>cm<sup>&#x2212;3</sup> at a minimum reverse blocking efficiency of &#x007E; 90&#x0025; extending well into high 10<sup>17</sup>cm<sup>&#x2212;3</sup> range (<inline-formula> <tex-math notation="LaTeX">$\sim \,\,8\times 10^{17}$ </tex-math></inline-formula>cm<sup>&#x2212;3</sup>). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.
topic Punchthrough (PT)
reverse blocking efficiency
silicon nitride shadowed selective-area growth (SNS-SAG)
space-modulated junction termination extension (SM-JTE)
url https://ieeexplore.ieee.org/document/9269357/
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