Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

Vertically stacked nanowire field effect transistors currently dominate the race to become mainstream devices for 7-nm CMOS technology node. However, these devices are likely to suffer from the issue of nanowire stack position dependent drain current. In this paper, we show that the nanowire located...

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Bibliographic Details
Main Authors: Anil Kumar Bansal, Ishita Jain, Terence B. Hook, Abhisek Dixit
Format: Article
Language:English
Published: IEEE 2016-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Nanowire
FinFET
CMOS
series resistance
TCAD
Online Access:https://ieeexplore.ieee.org/document/7526318/

Internet

https://ieeexplore.ieee.org/document/7526318/

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