A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

This paper presents a fully synthesizable successive-approximation-register (SAR) analog-to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generat...

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Bibliographic Details
Main Authors: Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Analog-to-digital converter
comparator
digital-to-analog converter
on-chip oscilloscope
redundant error correction
standard-cell-based design
Online Access:https://ieeexplore.ieee.org/document/8708173/

Internet

https://ieeexplore.ieee.org/document/8708173/

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