A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors
This paper presents a fully synthesizable successive-approximation-register (SAR) analog-to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generat...
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| Online Access: | https://ieeexplore.ieee.org/document/8708173/ |
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doaj-da67ede8e5514013b657086fb5a2da9b2021-03-29T22:56:24ZengIEEEIEEE Access2169-35362019-01-017636866369710.1109/ACCESS.2019.29153658708173A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform MonitorsJun-Eun Park0https://orcid.org/0000-0001-6345-7903Young-Ha Hwang1Deog-Kyoon Jeong2https://orcid.org/0000-0003-0436-703XBK21+ Creative Research Engineer Development for IT, Seoul National University, Seoul, South KoreaDepartment of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaDepartment of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaThis paper presents a fully synthesizable successive-approximation-register (SAR) analog-to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generation based on regular digital design tools. Therefore, the proposed ADC provides enhanced portability and reusability which facilitate integration into various functional blocks requiring testing and diagnosis. To implement the SAR ADC, a synthesizable voltage digital-to-analog converter (VDAC) and a rail-to-rail hybrid comparator are proposed in this paper. An inherited nonlinearity of the standard-cell-based VDAC is compensated by a histogram-based soft calibration which can be easily embedded in a waveform reconstruction module. In addition, an oversampling technique with a redundant error correction method is employed to realize the fully synthesizable design without a sample-and-hold (S/H) circuit. The proposed ADC was fabricated in 28-nm CMOS technology, occupying an active area of 0.002 mm<sup>2</sup>. The ADC achieves 5.39-bit effective-number-of-bit (ENOB) at 500-kS/s sampling rate. The power consumption of the ADC is 92.2 μW with a supply voltage of 0.5 V.https://ieeexplore.ieee.org/document/8708173/Analog-to-digital convertercomparatordigital-to-analog converteron-chip oscilloscoperedundant error correctionstandard-cell-based design |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Jun-Eun Park Young-Ha Hwang Deog-Kyoon Jeong |
| spellingShingle |
Jun-Eun Park Young-Ha Hwang Deog-Kyoon Jeong A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors IEEE Access Analog-to-digital converter comparator digital-to-analog converter on-chip oscilloscope redundant error correction standard-cell-based design |
| author_facet |
Jun-Eun Park Young-Ha Hwang Deog-Kyoon Jeong |
| author_sort |
Jun-Eun Park |
| title |
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors |
| title_short |
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors |
| title_full |
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors |
| title_fullStr |
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors |
| title_full_unstemmed |
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors |
| title_sort |
0.5-v fully synthesizable sar adc for on-chip distributed waveform monitors |
| publisher |
IEEE |
| series |
IEEE Access |
| issn |
2169-3536 |
| publishDate |
2019-01-01 |
| description |
This paper presents a fully synthesizable successive-approximation-register (SAR) analog-to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generation based on regular digital design tools. Therefore, the proposed ADC provides enhanced portability and reusability which facilitate integration into various functional blocks requiring testing and diagnosis. To implement the SAR ADC, a synthesizable voltage digital-to-analog converter (VDAC) and a rail-to-rail hybrid comparator are proposed in this paper. An inherited nonlinearity of the standard-cell-based VDAC is compensated by a histogram-based soft calibration which can be easily embedded in a waveform reconstruction module. In addition, an oversampling technique with a redundant error correction method is employed to realize the fully synthesizable design without a sample-and-hold (S/H) circuit. The proposed ADC was fabricated in 28-nm CMOS technology, occupying an active area of 0.002 mm<sup>2</sup>. The ADC achieves 5.39-bit effective-number-of-bit (ENOB) at 500-kS/s sampling rate. The power consumption of the ADC is 92.2 μW with a supply voltage of 0.5 V. |
| topic |
Analog-to-digital converter comparator digital-to-analog converter on-chip oscilloscope redundant error correction standard-cell-based design |
| url |
https://ieeexplore.ieee.org/document/8708173/ |
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