Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge rou...

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Bibliographic Details
Main Authors: Chandan Kumar Jha, Pritam Yogi, Charu Gupta, Anshul Gupta, Reinaldo A. Vega, Abhisek Dixit
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Line edge roughness
mismatch
nanosheet (NS)
auto-covariance function
CMOS scaling
Online Access:https://ieeexplore.ieee.org/document/9205251/

Internet

https://ieeexplore.ieee.org/document/9205251/

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