Conceptual Implementation of Sample Rate Convertors for DACs
One of most common and difficult challenge when creating a single SoC with digital (sub)sections is caused by the various master clock (MCLK) frequencies that each individual IC had originally. There are several methods to solve this, but when constraint by price and power consumption, the design...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Stefan cel Mare University of Suceava
2010-05-01
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| Series: | Advances in Electrical and Computer Engineering |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.4316/AECE.2010.02009 |