Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology
This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the...
Main Authors: | Rezapour Arash, Setoudeh Farbod, Tavakoli Mohammad Bagher |
---|---|
Format: | Article |
Language: | English |
Published: |
Sciendo
2019-12-01
|
Series: | Journal of Applied Engineering Sciences |
Subjects: | |
Online Access: | https://doi.org/10.2478/jaes-2019-0023 |
Similar Items
-
Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology
by: Rajendran, Dinesh Babu
Published: (2011) -
A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology
by: Jianwen Li, et al.
Published: (2020-02-01) -
Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters
by: Assaad, Rida Shawky
Published: (2011) -
CMOS Inverter as Analog Circuit: An Overview
by: Woorham Bae
Published: (2019-08-01) -
Low-power techniques for high-performance pipelined analog to digital converter
by: Lee, Byung-geun, 1973-
Published: (2008)