One electron-controlled multiple-valued dynamic random-access-memory
We propose a new architecture for a dynamic random-access-memory (DRAM) capable of storing multiple values by using a single-electron transistor (SET). The gate of a SET is designed to be connected to a plurality of DRAM unit cells that are arrayed at intersections of word lines and bitlines. In thi...
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
AIP Publishing LLC
2016-02-01
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| Series: | AIP Advances |
| Online Access: | http://dx.doi.org/10.1063/1.4942901 |