High-speed implementation of ANT series block cipher algorithm on FPGA

High-speed implementation of ANT series block cipher algorithm on FPGA

ANT series block cipher algorithm is suitable for lightweight implementation and convenient for side channel protection. For ANT-128/128 algorithm, Verilog HDL is used to implement the key expansion module and encryption module in Quartus II 15.0, and a 46-level pipeline structure is adopted for hig...

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Bibliographic Details
Main Authors: Wang Jianxin, Liu Ruian, Xiao Chaoen, Zhang Lei
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2021-04-01
Series:Dianzi Jishu Yingyong
Subjects:
ant
block cipher
verilog hdl
pipeline structure
Online Access:http://www.chinaaet.com/article/3000130960

Internet

http://www.chinaaet.com/article/3000130960

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