Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction
In modular distributed architectures, the adoption of a communication method that is at the same time robust and has a low and predictable latency is of utmost importance in order to support the required system dynamics. The aim of this paper is to evaluate the consequences of the random jitter on m...
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MDPI AG
2020-02-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/2/281 |
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doaj-e67c11612ebb451bb7e97655bd45f3b12020-11-25T01:12:58ZengMDPI AGElectronics2079-92922020-02-019228110.3390/electronics9020281electronics9020281Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error CorrectionValentina Bianchi0Filippo Savi1Ilaria De Munari2Davide Barater3Giampaolo Buticchi4Giovanni Franceschini5Department of Engineering and Architecture, University of Parma, Parco Area delle Scienze, 181/A, 43124 Parma, ItalyFaculty of Science and Engineering, University of Nottingham Ningbo, 199 Taikang East Road, Ningbo 315100, ChinaDepartment of Engineering and Architecture, University of Parma, Parco Area delle Scienze, 181/A, 43124 Parma, ItalyDepartment of Engineering “Enzo Ferrari”, University of Modena and Reggio Emilia, lVia P. Vivarelli, 10, 41125 Modena, ItalyFaculty of Science and Engineering, University of Nottingham Ningbo, 199 Taikang East Road, Ningbo 315100, ChinaDepartment of Engineering “Enzo Ferrari”, University of Modena and Reggio Emilia, lVia P. Vivarelli, 10, 41125 Modena, ItalyIn modular distributed architectures, the adoption of a communication method that is at the same time robust and has a low and predictable latency is of utmost importance in order to support the required system dynamics. The aim of this paper is to evaluate the consequences of the random jitter on machine drives distributed control, caused by the messages’ re-transmission in case of an error in the received data. To achieve this goal, two different Forward Error Correction (FEC) techniques are introduced in the chosen protocol, so that the recipient of the message can correct random errors without the need of any additional round trip delays needed to request and obtain a re-transmission. Experimentally validated simulations are used to evaluate the impact of random network derived jitter on a real world closed loop control system for distributed power electronic converters.https://www.mdpi.com/2079-9292/9/2/281modular power convertersfield programmable gate array (fpga)faulttoleranceerror correction codesdigital communications |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Valentina Bianchi Filippo Savi Ilaria De Munari Davide Barater Giampaolo Buticchi Giovanni Franceschini |
| spellingShingle |
Valentina Bianchi Filippo Savi Ilaria De Munari Davide Barater Giampaolo Buticchi Giovanni Franceschini Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction Electronics modular power converters field programmable gate array (fpga) faulttolerance error correction codes digital communications |
| author_facet |
Valentina Bianchi Filippo Savi Ilaria De Munari Davide Barater Giampaolo Buticchi Giovanni Franceschini |
| author_sort |
Valentina Bianchi |
| title |
Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction |
| title_short |
Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction |
| title_full |
Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction |
| title_fullStr |
Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction |
| title_full_unstemmed |
Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction |
| title_sort |
minimization of network induced jitter impact on fpga-based control systems for power electronics through forward error correction |
| publisher |
MDPI AG |
| series |
Electronics |
| issn |
2079-9292 |
| publishDate |
2020-02-01 |
| description |
In modular distributed architectures, the adoption of a communication method that is at the same time robust and has a low and predictable latency is of utmost importance in order to support the required system dynamics. The aim of this paper is to evaluate the consequences of the random jitter on machine drives distributed control, caused by the messages’ re-transmission in case of an error in the received data. To achieve this goal, two different Forward Error Correction (FEC) techniques are introduced in the chosen protocol, so that the recipient of the message can correct random errors without the need of any additional round trip delays needed to request and obtain a re-transmission. Experimentally validated simulations are used to evaluate the impact of random network derived jitter on a real world closed loop control system for distributed power electronic converters. |
| topic |
modular power converters field programmable gate array (fpga) faulttolerance error correction codes digital communications |
| url |
https://www.mdpi.com/2079-9292/9/2/281 |
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