Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications
In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain...
Main Authors: | T. Suguna, M. Janaki Rani |
---|---|
Format: | Article |
Language: | English |
Published: |
International Association of Online Engineering (IAOE)
2020-04-01
|
Series: | International Journal of Interactive Mobile Technologies |
Subjects: | |
Online Access: | https://online-journals.org/index.php/i-jim/article/view/13343 |
Similar Items
-
Implementation of Pipelined Bit-parallel Adders
by: Wei, Lan
Published: (2003) -
Synthesis of 64 bit Energy Efficient and Reconfigurable Adder
by: Dara, chandra babu
Published: (2009) -
A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization
by: Muhammad Ali Akbar, et al.
Published: (2021-07-01) -
Fast Mux-based Adder with Low Delay and Low PDP
by: H. Tavakolaee, et al.
Published: (2019-07-01) -
Pipelined Two-Operand Modular Adders
by: M. Czyzak, et al.
Published: (2015-04-01)