FPGA-Based Hardware Matrix Inversion Architecture Using Hybrid Piecewise Polynomial Approximation Systolic Cells

FPGA-Based Hardware Matrix Inversion Architecture Using Hybrid Piecewise Polynomial Approximation Systolic Cells

The hardware of the matrix inversion architecture using QR decomposition with Givens Rotations (GR) and a back substitution (BS) block is required for many signal processing algorithms. However, the hardware of the GR algorithm requires the implementation of complex operations, such as the reciproca...

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Bibliographic Details
Main Authors: Javier Vázquez-Castillo, Alejandro Castillo-Atoche, Roberto Carrasco-Alvarez, Omar Longoria-Gandara, Jaime Ortegón-Aguilar
Format: Article
Language:English
Published: MDPI AG 2020-01-01
Series:Electronics
Subjects:
field programmable gate arrays
matrix inversion
piecewise polynomial approximation
qr decomposition
systolic arrays
Online Access:https://www.mdpi.com/2079-9292/9/1/182

Internet

https://www.mdpi.com/2079-9292/9/1/182

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