Via placement optimization for a group of wires
Most PCB design CAD systems offer a limited number of “patterns” for the via placement on a bus (group of wires) which would be either a single- or a double-row placement. This article demonstrates the incorrectness of such limitations, because in this case the mounting space is used not in an optim...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Politehperiodika
2015-06-01
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| Series: | Tekhnologiya i Konstruirovanie v Elektronnoi Apparature |
| Subjects: | |
| Online Access: | http://www.tkea.com.ua/tkea/2015/2-3_2015/pdf/02.pdf |