Parasitic-Based Active Gate Driver Improving the Turn-On Process of 1.7 kV SiC Power MOSFET

• Main Authors: Bartosz Lasek, Przemysław Trochimiuk, Rafał Kopacz, Jacek Rąbkowski
• Format: Article
• Language: English
• Published: MDPI AG 2021-03-01
• Series: Applied Sciences
• Subjects: active gate driver; medium voltage; power losses; SiC MOSFET
• Online Access: https://www.mdpi.com/2076-3417/11/5/2210

This article discusses an active gate driver for a 1.7 kV/325 A SiC MOSFET module. The main purpose of the driver is to adjust the gate voltage in specified moments to speed up the turn-on cycle and reduce the amount of dissipated energy. Moreover, an adequate manipulation of the gate voltage is necessary as the gate current should be reduced during the rise of the drain current to avoid overshoots and oscillations. The gate voltage is switched at the right moments on the basis of the feedback signal provided from a measurement of the voltage across the parasitic source inductance of the module. This approach simplifies the circuit and provides no additional power losses in the measuring circuit. The paper contains the theoretical background and detailed description of the active gate driver design. The model of the parasitic-based active gate driver was verified using the double-pulse procedure both in Saber simulations and laboratory experiments. The active gate driver decreases the turn-on energy of a 1.7 kV/325 A SiC MOSFET by 7% comparing to a conventional gate driver (<i>V</i>_DS = 900 V, <i>I</i>_D = 270 A, <i>R</i>_G = 20 Ω). Furthermore, the proposed active gate driver lowered the turn-on cycle time from 478 to 390 ns without any serious oscillations in the main circuit.