FPGA-based structurally improved(2，1，4) Viterbi decoder
The implementation of high-performance Viterbi decoding algorithm in resource-constrained processors is a hot topic in recent years. This paper is based on the XC6SLX16-2CSG324 type FPGA processor. In the case of limited resources, in order to balance the problem of Viterbi decoding delay and resour...
| Main Authors: | , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2020-02-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000114726 |