FPGA-based structurally improved(2，1，4) Viterbi decoder

• Main Authors: Wu Xueling, Jiang Hong
• Format: Article
• Language: zho
• Published: National Computer System Engineering Research Institute of China 2020-02-01
• Series: Dianzi Jishu Yingyong
• Subjects: fpga; viterbi decoder; metric control; stepped storage structure
• Online Access: http://www.chinaaet.com/article/3000114726

The implementation of high-performance Viterbi decoding algorithm in resource-constrained processors is a hot topic in recent years. This paper is based on the XC6SLX16-2CSG324 type FPGA processor. In the case of limited resources, in order to balance the problem of Viterbi decoding delay and resource consumption, an improved algorithm is proposed. On the basis of the traditional Viterbi decoding algorithm, the purpose of controlling the path metric value is achieved by maximizing the pre-defined storage path metric value register, and then the stepped survivor path information storage structure is used to complete the storage of the surviving path information and simplifying the decoder hardware implements complexity, reducing decoding delay and resource consumption. Based on the ISE Design Suite 14.7 platform, FPGA-based verification of(2，1，4)-dimensional bit decoders with 20- and 3-bit soft-decision depths is performed, and combined with MATLAB simulation. The results show that the method can effectively reduce the decoding delay and reduce the resource consumption.