Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS

Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS

Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameter...

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Bibliographic Details
Main Authors: Tara Ghafouri, Negin Manavizadeh
Format: Article
Language:English
Published: Elsevier 2020-10-01
Series:Alexandria Engineering Journal
Subjects:
6T static random-access memory (SRAM) bit-cell
Side-contacted field effect diode (S-FED)
Static noise margin
Power dissipation
Sensitivity analyses
Online Access:http://www.sciencedirect.com/science/article/pii/S1110016820302945

Internet

http://www.sciencedirect.com/science/article/pii/S1110016820302945

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