Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS
Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameter...
Main Authors: | , |
---|---|
Format: | Article |
Language: | English |
Published: |
Elsevier
2020-10-01
|
Series: | Alexandria Engineering Journal |
Subjects: | |
Online Access: | http://www.sciencedirect.com/science/article/pii/S1110016820302945 |
id |
doaj-f0547c135ad7464d8410506c74cfacad |
---|---|
record_format |
Article |
spelling |
doaj-f0547c135ad7464d8410506c74cfacad2021-06-02T15:23:29ZengElsevierAlexandria Engineering Journal1110-01682020-10-0159537153729Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOSTara Ghafouri0Negin Manavizadeh1Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran 1631714191, IranCorresponding author.; Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran 1631714191, IranDesigning a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED) and conventional CMOS at 180 nm technology node. Steady-state responses demonstrate that in the worst-case, by applying weak logic 0/1 to the bit-lines, strong logic data is stored in the S-FED-based cell with superior write margin and lower power consumption by about one order of magnitude in comparison with the CMOS-based one. Comparing static noise margin reveals that S-FED-based cells enjoy prominent stability, especially in the read and hold operations with ~3X and 29% improvements, respectively, to the CMOS-based versions. In addition, enhancement of read-stability is attained utilizing S-FED-based cell, as well as decrement of subthreshold current and static power dissipation, compared with the CMOS-based one. Sensitivity analyses extracted from Monte Carlo simulations and butterfly curves indicate that S-FED-based cell successfully tolerates process and supply voltage variations in all operation modes, superior to the CMOS-based counterpart.http://www.sciencedirect.com/science/article/pii/S11100168203029456T static random-access memory (SRAM) bit-cellSide-contacted field effect diode (S-FED)Static noise marginPower dissipationSensitivity analyses |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Tara Ghafouri Negin Manavizadeh |
spellingShingle |
Tara Ghafouri Negin Manavizadeh Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS Alexandria Engineering Journal 6T static random-access memory (SRAM) bit-cell Side-contacted field effect diode (S-FED) Static noise margin Power dissipation Sensitivity analyses |
author_facet |
Tara Ghafouri Negin Manavizadeh |
author_sort |
Tara Ghafouri |
title |
Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS |
title_short |
Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS |
title_full |
Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS |
title_fullStr |
Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS |
title_full_unstemmed |
Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS |
title_sort |
performance comparison of 6t sram bit-cells based on side-contacted fed and cmos |
publisher |
Elsevier |
series |
Alexandria Engineering Journal |
issn |
1110-0168 |
publishDate |
2020-10-01 |
description |
Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED) and conventional CMOS at 180 nm technology node. Steady-state responses demonstrate that in the worst-case, by applying weak logic 0/1 to the bit-lines, strong logic data is stored in the S-FED-based cell with superior write margin and lower power consumption by about one order of magnitude in comparison with the CMOS-based one. Comparing static noise margin reveals that S-FED-based cells enjoy prominent stability, especially in the read and hold operations with ~3X and 29% improvements, respectively, to the CMOS-based versions. In addition, enhancement of read-stability is attained utilizing S-FED-based cell, as well as decrement of subthreshold current and static power dissipation, compared with the CMOS-based one. Sensitivity analyses extracted from Monte Carlo simulations and butterfly curves indicate that S-FED-based cell successfully tolerates process and supply voltage variations in all operation modes, superior to the CMOS-based counterpart. |
topic |
6T static random-access memory (SRAM) bit-cell Side-contacted field effect diode (S-FED) Static noise margin Power dissipation Sensitivity analyses |
url |
http://www.sciencedirect.com/science/article/pii/S1110016820302945 |
work_keys_str_mv |
AT taraghafouri performancecomparisonof6tsrambitcellsbasedonsidecontactedfedandcmos AT neginmanavizadeh performancecomparisonof6tsrambitcellsbasedonsidecontactedfedandcmos |
_version_ |
1721403315224313856 |