DESIGN OF STANDARD CELL ASIC’S USING SELF GATED RESONANT CLOCKED FLIP FLOP
Efforts to reduce power consumption of digital CMOS circuits have been in progress for nearly three decades. As a result, a number of well understood and proven techniques for reducing dynamic and leakage power have been developed. These methods are implemented thoroughly in the circuit level. S...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2020-03-01
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| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_Vol_3_Iss_2_Paper_2_385_388.pdf |