A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling freq...

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Bibliographic Details
Main Authors: Hyungyu Ju, Minjae Lee
Format: Article
Language:English
Published: MDPI AG 2019-02-01
Series:Electronics
Subjects:
asynchronous
delay cell
passive resistor
SAR ADC
loop delay circuit
Online Access:https://www.mdpi.com/2079-9292/8/3/262

Internet

https://www.mdpi.com/2079-9292/8/3/262

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