Parasitic Current Induced by Gate Overlap in Thin-Film Transistors
As novel applications of oxide semiconductors are realized, various structural devices and integrated circuits are being proposed, and the gate-overlay defect phenomenon is becoming more diverse in its effects. Herein, the electrical properties of the transistor that depend on the geometry between t...
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doaj-f2ec65b2ea3d438990edc6db2378c6aa2021-04-29T23:01:18ZengMDPI AGMaterials1996-19442021-04-01142299229910.3390/ma14092299Parasitic Current Induced by Gate Overlap in Thin-Film TransistorsHyeon-Jun Lee0Katsumi Abe1June-Seo Kim2Won-Seok Yun3Myoung-Jae Lee4Institute of Convergence, Daegu Gyeonbuk Institute of Science & Technology (DGIST), Daegu 42988, KoreaSilvaco Japan Co., Ltd., Nakagyo-ku, Kyoto 604-8152, JapanInstitute of Convergence, Daegu Gyeonbuk Institute of Science & Technology (DGIST), Daegu 42988, KoreaInstitute of Convergence, Daegu Gyeonbuk Institute of Science & Technology (DGIST), Daegu 42988, KoreaInstitute of Convergence, Daegu Gyeonbuk Institute of Science & Technology (DGIST), Daegu 42988, KoreaAs novel applications of oxide semiconductors are realized, various structural devices and integrated circuits are being proposed, and the gate-overlay defect phenomenon is becoming more diverse in its effects. Herein, the electrical properties of the transistor that depend on the geometry between the gate and the semiconductor layer are analyzed, and the specific phenomena associated with the degree of overlap are reproduced. In the semiconductor layer, where the gate electrode is not overlapped, it is experimentally shown that a dual current is generated, and the results of 3D simulations confirm that the magnitude of the current increases as the parasitic current moves away from the gate electrode. The generation and path of the parasitic current are then represented visually through laser-enhanced 2D transport measurements; consequently, the flow of the dual current in the transistor is verified to be induced by the electrical potential imbalance in the semiconductor active layer, where the gate electrodes do not overlap.https://www.mdpi.com/1996-1944/14/9/2299oxide semiconductor<i>a</i>-IGZObarrier loweringhump |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Hyeon-Jun Lee Katsumi Abe June-Seo Kim Won-Seok Yun Myoung-Jae Lee |
spellingShingle |
Hyeon-Jun Lee Katsumi Abe June-Seo Kim Won-Seok Yun Myoung-Jae Lee Parasitic Current Induced by Gate Overlap in Thin-Film Transistors Materials oxide semiconductor <i>a</i>-IGZO barrier lowering hump |
author_facet |
Hyeon-Jun Lee Katsumi Abe June-Seo Kim Won-Seok Yun Myoung-Jae Lee |
author_sort |
Hyeon-Jun Lee |
title |
Parasitic Current Induced by Gate Overlap in Thin-Film Transistors |
title_short |
Parasitic Current Induced by Gate Overlap in Thin-Film Transistors |
title_full |
Parasitic Current Induced by Gate Overlap in Thin-Film Transistors |
title_fullStr |
Parasitic Current Induced by Gate Overlap in Thin-Film Transistors |
title_full_unstemmed |
Parasitic Current Induced by Gate Overlap in Thin-Film Transistors |
title_sort |
parasitic current induced by gate overlap in thin-film transistors |
publisher |
MDPI AG |
series |
Materials |
issn |
1996-1944 |
publishDate |
2021-04-01 |
description |
As novel applications of oxide semiconductors are realized, various structural devices and integrated circuits are being proposed, and the gate-overlay defect phenomenon is becoming more diverse in its effects. Herein, the electrical properties of the transistor that depend on the geometry between the gate and the semiconductor layer are analyzed, and the specific phenomena associated with the degree of overlap are reproduced. In the semiconductor layer, where the gate electrode is not overlapped, it is experimentally shown that a dual current is generated, and the results of 3D simulations confirm that the magnitude of the current increases as the parasitic current moves away from the gate electrode. The generation and path of the parasitic current are then represented visually through laser-enhanced 2D transport measurements; consequently, the flow of the dual current in the transistor is verified to be induced by the electrical potential imbalance in the semiconductor active layer, where the gate electrodes do not overlap. |
topic |
oxide semiconductor <i>a</i>-IGZO barrier lowering hump |
url |
https://www.mdpi.com/1996-1944/14/9/2299 |
work_keys_str_mv |
AT hyeonjunlee parasiticcurrentinducedbygateoverlapinthinfilmtransistors AT katsumiabe parasiticcurrentinducedbygateoverlapinthinfilmtransistors AT juneseokim parasiticcurrentinducedbygateoverlapinthinfilmtransistors AT wonseokyun parasiticcurrentinducedbygateoverlapinthinfilmtransistors AT myoungjaelee parasiticcurrentinducedbygateoverlapinthinfilmtransistors |
_version_ |
1721500264333049856 |