Double Edge-Triggered Half-Static Clock-Gating D-Type Flip-Flop
A double edge-triggered D-type flip flop includes a half-static clock gating circuit is presented in this paper. Two dynamic latches that each responses to the rising and falling edges of the gated clock are connected in parallel to a half-static latch, which captures the data signal in response to...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
KeAi Communications Co., Ltd.
2021-12-01
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| Series: | Solid State Electronics Letters |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2589208821000077 |