A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain
A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2020-03-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/9/3/507 |