Equivalence Checking of Scheduling in High-Level Synthesis Using Deep State Sequences

Equivalence Checking of Scheduling in High-Level Synthesis Using Deep State Sequences

By using high-level synthesis tools, electronic system level design provides a promising solution to fill the growing design productivity gap of high quality hardware systems. However, an error may exist in the implementation of a compiler due to the complex and error prone compiling process. Equiva...

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Bibliographic Details
Main Authors: Jian Hu, Guanwu Wang, Guilin Chen, Xianglin Wei
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Equivalence checking
high-level synthesis
deep state sequence
FSMD
Online Access:https://ieeexplore.ieee.org/document/8936448/

Internet

https://ieeexplore.ieee.org/document/8936448/

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