Characterization and Modeling of Mismatch in Cryo-CMOS

Characterization and Modeling of Mismatch in Cryo-CMOS

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mis...

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Bibliographic Details
Main Authors: P. A. T Hart, M. Babaie, Edoardo Charbon, Andrei Vladimirescu, Fabio Sebastiano
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Mismatch
cryogenics
MOSFETs
Cryo-CMOS
modeling
stress
Online Access:https://ieeexplore.ieee.org/document/9015956/

Internet

https://ieeexplore.ieee.org/document/9015956/

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