An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates
Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present,...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2015-01-01
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| Series: | The Scientific World Journal |
| Online Access: | http://dx.doi.org/10.1155/2015/621012 |