Management of Load-Balancing Data Stream in Interposer-Based Network-on-Chip Using Specific Virtual Channels
The interaction between cores and memory blocks, in multiprocessor chips and smart systems, has always been a concern as it affects network latency, memory capacity, and power consumption. A new 2.5-dimensional architecture has been introduced in which the communication between the processing elemen...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi-Wiley
2020-01-01
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| Series: | Wireless Communications and Mobile Computing |
| Online Access: | http://dx.doi.org/10.1155/2020/8887589 |