PACoGen: A Hardware Posit Arithmetic Core Generator

PACoGen: A Hardware Posit Arithmetic Core Generator

This paper proposes open-source hardware Posit Arithmetic Core Generator (PACoGen) for the recently developed universal number posit number system, along with a set of pipelined architectures. The posit number system composed of a run-time varying exponent component, which is defined by a compositio...

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Bibliographic Details
Main Authors: Manish Kumar Jaiswal, Hayden K.-H. So
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Adder
ASIC
digital arithmetic
division
floating point arithmetic
FPGA
Online Access:https://ieeexplore.ieee.org/document/8731915/

Internet

https://ieeexplore.ieee.org/document/8731915/

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