Memory Compact High-Speed QC-LDPC Decoder Based on FPGA
In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates m...
| Format: | Article |
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| Language: | zho |
| Published: |
The Northwestern Polytechnical University
2019-06-01
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| Series: | Xibei Gongye Daxue Xuebao |
| Subjects: | |
| Online Access: | https://www.jnwpu.org/articles/jnwpu/full_html/2019/03/jnwpu2019373p515/jnwpu2019373p515.html |