Automatic simulation method for functional equivalence check

Automatic simulation method for functional equivalence check

In the mixed-signal chip, behavioral model is widely used to describe the behavior of the analog/mixed-signal blocks in Verilog/Systemverilog/VHDL so as to facilitate the fullchip netlisting for the fullchip Verilog simulation. In order to ensure correct，effective and comprehensine function verifica...

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Bibliographic Details
Main Authors: Liao Lu, Hou Chunyuan, Li Yueping, Wang Mei, Liu Huanyan, Huang Chengquan, Xu Nannan, Dong Lixia
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2019-08-01
Series:Dianzi Jishu Yingyong
Subjects:
functional equivalence check
bvs
wreal modeling
real type vector check
xps
Online Access:http://www.chinaaet.com/article/3000107412

Internet

http://www.chinaaet.com/article/3000107412

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