MCML D-Latch Using Triple-Tail Cells: Analysis and Design
A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its s...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2013-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/2013/217674 |