Low Error Efficient Approximate Adders for FPGAs

Low Error Efficient Approximate Adders for FPGAs

In this paper, we propose a methodology for designing low error efficient approximate adders for FPGAs. The proposed methodology utilizes FPGA resources efficiently to reduce the error of approximate adders. We propose two approximate adders for FPGAs using our methodology: low error and area effici...

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Bibliographic Details
Main Authors: Waqar Ahmad, Berke Ayrancioglu, Ilker Hamzaoglu
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Approximate computing
approximate adder
FPGA
low error
low power
LUT
Online Access:https://ieeexplore.ieee.org/document/9521486/

Internet

https://ieeexplore.ieee.org/document/9521486/

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