Asynchronous Early Output Dual-bit Full Adders Based on Homogeneous and Heterogeneous Delay-insensitive Data Encoding
This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive data encoding only dual-rail i.e. 1-of-2 code is used, and f...
| Main Authors: | , |
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| Format: | Others |
| Published: |
World Scientific and Engineering Academy and Society,
2017-07-26T23:47:02Z.
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| Subjects: | |
| Online Access: | Get fulltext |