Arithmetic logic unit design for silicon nanowire field-effect transistors logic
As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gat...
| Main Author: | |
|---|---|
| Format: | Thesis |
| Published: |
2015-01.
|
| Subjects: | |
| Online Access: | Get fulltext |