Design and performance evaluation of a low-power data-line SRAM sense amplifier
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bit-and data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 à ¿m CMOS standard process from Chartered Semiconductor Manuf...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers,
2010-10-15T14:43:49Z.
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| Subjects: | |
| Online Access: | Get fulltext |