Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects
In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, we explore the design of energy-efficient low-diameter networks (flattene...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers,
2010-10-20T12:44:48Z.
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| Subjects: | |
| Online Access: | Get fulltext |